1. Field of the Invention
The present invention relates to a flat panel display, and in particular to a flat panel display and an operation method thereof which are capable of lowering a capacitance of a pixel cell.
2. Description of the Prior Art
Recently, various flat display devices having a light weight and a small volume of a CRT (cathode ray tube) have been developed. There are a LCD (liquid crystal display), a FED (field emission display), a plasma display panel and an electro-luminescence, etc. In order to improve a display quality, researches and developments in brightness, contrast and colorimetric purity of a flat display device have been performed actively.
The FED (field emission display) is divided into a tip type FED (field emission display) emitting electrons by concentrating a high electric field to an acuminate emitter by using a quantum-mechanical tunnel effect and a MIM (metal insulator metal) type FED (field emission display) emitting electrons by concentrating a high electric field to a metal having a certain area by using a quantum-mechanical tunnel effect.
FIG. 1 is a perspective view illustrating the conventional tip type FED (field emission display).
FIG. 2 is a sectional view illustrating the tip type FED (field emission display) of FIG. 1.
As depicted in FIGS. 1 and 2, the tip type FED (field emission display) includes an upper glass substrate 2 laminated an anode electrode 4 and a phosphor 6 and an electric field emission array 32 formed on a lower glass substrate 8. The electric field emission array 32 is constructed with a cathode electrode 10 and a resistance layer 12 formed on the lower glass substrate 8, a gate insulating layer 14 and an emitter 22 formed on the resistance layer 12 and a gate electrode 16 formed on the gate insulating layer 14.
The cathode electrode 10 supplies a current to the emitter 22, the resistance layer 12 restricts an exceed current applied from the cathode electrode 10 to the emitter 22 in order to supply a uniform current to the emitter 22.
The gate insulating layer 14 insulates the cathode electrode 10 and the gate electrode 16. The gate electrode 16 is used as an emission electrode for emitting electrons. A spacer 40 is installed between the upper glass substrate 2 and the lower glass substrate 8.
The spacer 40 supports the upper glass substrate 2 and the lower glass substrate 8 so as to maintain a high vacuum state between them.
In order to display a picture, a −cathode voltage is applied to the cathode electrode 10, and +anode voltage is applied to the anode electrode 4. And, +gate voltage is applied to the gate electrode 16. Then, an electron beam 30 emitted from the emitter 22 clashes against the RGB (red•green•blue) phosphor 6, accordingly the phosphor 6 is excited. Herein, a visible light as one of red•green•blue•colors is emitted according to the phosphor 6.
In the above-described tip type FED (field emission display), a quantity of emitted electrons is determined according to characteristics of an emitter used in electron emission. Accordingly, all emitters included in one FED have to be made uniformly. However, in the present production process, it is difficult to make all emitters have uniform characteristics. In addition, lots of production time is required to produce an emitter.
In addition, in the tip type FED (field emission display), because electrons are emitted from the acuminate emitter, it is difficult to reduce a gap between the cathode electrode 10 and the gate electrode 16, accordingly a high voltage as 30 ˜100 volt has to be applied between the two electrodes.
Therefore, power consumption is high due to the voltage applied to the cathode electrode 10 and the gate electrode 16.
FIGS. 3A and 3B illustrate a pixel cell of the conventional MIM (metal insulator metal) type FED (field emission display).
As depicted in FIGS. 3A and 3B, a pixel cell of the MIM type FED (field emission display) is constructed with an upper substrate 42 laminated an anode electrode 44 and a phosphor 46 and an electric field emission array 56 formed on a lower substrate 48.
The electric field emission array 56 is constructed with a scan electrode 50, an insulating layer 52 and a data electrode 54 formed on the lower substrate 48.
In order to display a picture, −scan pulse is applied to the scan electrode 50, and +data pulse is applied to the data electrode 54. And, +anode voltage is applied to the anode electrode 44. Then, tunneling of electrons from the scan electrode 50 to the data electrode occurs, accordingly the electrons are accelerative toward the anode electrode 44.
The electrons clash against the RGB phosphor 46, and the phosphor 46 is excited. Herein, a visible light as one of red•green•blue colors is emitted according to the phosphor 46.
In the above-described MIM type FED (field emission display), because a distance between the scan electrode 50 and the data electrode 54 is very near in comparison with the tip type FED (field emission display), it is possible to fabricate an insulating layer as a thin layer, accordingly it can be operated at a voltage lower than a voltage of the tip type FED (field emission display). In other words, voltage as 3˜10 volt is applied to the scan electrode 50 and the data electrode 54 of the MIM type FED (field emission display). In addition, in the MIM type FED (field emission display), because the scan electrode 50 and the data electrode 54 emitting electrons have a certain area, it is possible to fabricate the scan electrode 50 and the data electrode 54 by a simple fabrication process in comparison with the tip type FED.
FIG. 4 is a wave diagram illustrating an operational wave supplied to the conventional MIM type FED (field emission display).
As depicted in FIG. 4, in the conventional MIM (metal insulator metal) type FED (field emission display), −scan pulse (SP) is sequentially supplied to a scan line (S), and +data pulse (DP) synchronized with the −scan pulse (SP) is supplied to a data line (D). A pixel cell receiving the scan pulse (SP) and the data pulse (DP) emits electrons by a voltage difference between the scan pulse (SP) and the data pulse (DP). It will be described in more detail with reference to accompanying FIG. 5.
FIG. 5 illustrates a FED (field emission display) at which pixel cells of FIGS. 3A and 3B are arranged as a matrix format.
As depicted in FIG. 5, when −5V scan pulse (SP) is applied to a first scan line (S1) and 5V data pulse (DP) is applied to the data line (D), a voltage difference as 10V is generated in first pixel cells (P1) formed at the first scan line (S1). Accordingly, electrons are emitted from the first pixel cells (P1). Herein, by supplying different data value to cells (D1˜Dn) of the data line (D), each pixel cell can be on/off. In more detail, each pixel cell placed at a cross point of the scan line(S1) and the cells (D1˜Dn) of the data line (D) is on/off according to a data line value.
Herein, a width and/or amplitude of the data pulse (DP) can be differently set according to a gray scale. For example, in description of a high gray scale, a width and/or amplitude of the data pulse (DP) is set as wide and/or high, in description of a low gray scale, a width and/or amplitude of the data pulse (DP) is set as narrow and/or low.
In the meantime, only data pulse (DP) is applied to second˜mth pixel cells (P2˜Pm) formed on second˜mth scan lines (S2˜Sm), electrons are not emitted from the second˜mth pixel cells (P2˜Pm).
After that, a picture can be displayed by operating the first˜the mth pixel cells (P1˜Pm) by sequentially applying the scan pulse (SP) and the data pulse (DP) (herein, DP is a whole value of D1˜Dn) up to the mth scan line (Sm). After displaying the picture, +reset pulse (RP) is applied to the first˜the mth scan lines (S1˜Sm). Then, electric charges charged in the first˜the mth pixel cells (P1˜Pm) are eliminated.
However, as depicted in FIGS. 3A and 3b, in the MIM type FED (field emission display) constructed with the scan electrode 50, the insulating layer 52 and the data electrode 50, the insulating layer 52 as an intermediate layer is very thin. In more detail, in C=∈×s/d (herein, ∈ is a dielectric constant, d is a dielectric constant width and s is a cell area), because a dielectric substance layer is very thin, “C” element is largely increased. In more detail, because it is constructed as a capacitor structure, a pixel cell (P) has a high capacitance. Particularly, when the scan pulse (SP) is supplied to the all pixel cells (D1˜Dn) formed on one scan line (S), an operational velocity is lowered by a capacitance value of the pixel cells (D1˜Dn). In addition, a voltage drop occurs due to a high current.
For example, when the scan pulse (SP) is supplied to a MIM type FED (field emission display) of 1920×480, the scan pulse (SP) and the data pulse (DP) are supplied to 1920 pixel cells. Herein, the pixel cells receiving the scan pulse (SP) and the data pulse (DP) have a certain capacitance value, the scan line (S) has a capacitance adding each capacitance value of the 1920 pixel cells. Accordingly, in the conventional MIM type FED (field emission display), a high velocity operation can not be performed due to a high capacitance. In more detail, it is difficult to perform a high velocity operation in the MIM type FED (field emission display) having a large screen.